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Supertex inc.
HV7100
Initial Release
24V/48V Fan Driver/Controller With High-Side Drive
Features
High-side drive allows use of tachs Direct interface to host controller Noise-immune linear speed control 4-bit digital speed control Operates from single +24V/+48V supply Programmable PWM frequency Undervoltage lockout
General Description
The HV7100 is an integrated PWM speed controller for driving 24V and 48V DC Fans. The features and benefits provided by the HV7100 make driving fans simple and low cost. The HV7100 drives a high side external P-channel FET, allowing the use of fans having a ground-based tachometer signal. It has a wide input voltage range of +16V to +90V, ideal for +24V or +48V systems. No low voltage supply is needed. A 4-bit digital control input provides direct interfacing with a microcontroller or system processor to control the fan speed. It can also be used as a stand-alone fan controller, via a thermistor connection to the Linear Control pin. The HV7100 has a wide PWM frequency range. When driving fans directly with a PWM supply voltage, frequency may be set low, around 50Hz - 120Hz. When used to drive fans requiring a DC supply, an LC filter may be employed. In this case, PWM frequency may be as high as 100kHz, reducing component sizes in the filter. The HV7100 is an ideal device to incorporate in fan trays and fan control modules, as it reduces circuit complexity and minimizes parts count and overall cost for thermal management.
Applications
24V/48V chassis cooling tray Servers SAN equipment Cellular and fix wireless systems 24V/48V PBX system Base stations
Typical Application Circuit
VPP
VPP1 speed control
VPP2
VGATE DIN0 - DIN3
enable
HV7100
EN LIN OUT CT RT VDD GND
Optional LC filter for providing a DC fan drive.
Host Controller
tach signals
Supertex inc.
* 1235 Bordeaux Drive, Sunnyvale, CA 94089 * Tel: (408) 222-8888 * FAX: (408) 222-4895 * www.supertex.com
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HV7100
Ordering Information
Package Options DEVICE 14-Pin SO HV7100 HV7100NG-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
VPP to GND VDD to GND Input Voltage, LIN Input Voltage , DIN0-DIN2 GATE to VPP Continuous Power Dissipation (TA = +25C) 14-Lead SO Operating Temperature Range Storage Temperature Range -0.5V to 90V -0.3V to +6V -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) +0.5V to -15V 750mW -40C to +85C -65C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol VDD VPP fOSC RT Parameter Externally applied VDD High voltage supply Oscillator frequency Oscillator timing resistor Min 3.7 16 50 12 Typ Max 5.5 75 100k 500 Units V V Hz k
Electrical Characteristics
(Operating specifications are at TA = 25C, VPP = 16V to 75V, VDD = 3.0V to 5.5V, unless otherwise noted) Symbol Supplies IPP UVPP(ON) UVPP(HYS) VDD IDD(INT) IDD(EXT) VPP supply current VPP UVLO turn-on threshold VPP UVLO hysteresis VDD internal regulation VDD supply current Current available from internal VDD regulator for external circuitry 11.7 1.5 3.0 13.0 2.0 3.3 4 14.3 2.5 3.6 2 mA V V V mA No ext load on VDD, fOSC = 50kHz, 250pF on OUT pin ----VPP = 16V to 75V External applied VDD = 5.0V, fOSC = 50kHz VDD<200mV Parameter Min Typ Max Units Conditions
-
-
2
mA
2
HV7100
Symbol Gate Driver VGATE VOUTH VOUTL RSRC RSINK tRISE tFALL Oscillator fOSC fOSC Oscillator frequency Oscillator frequency 51 34 60 40 69 46 Hz kHz CT = 100nF, RT = 43.0kohm CT = 330pF, RT = 19.5kohm Gate regulator output voltage Gate drive output voltage high Gate drive output voltage low Pull-up resistance Pull-down resistance Rise time Fall time -10.2 -10.2 0 -12 -12 -13.8 -13.8 -0.8 25 25 100 100 V V V ns ns Referenced to VPP, test current = 15mA Test Current = 15mA Test Current = -15mA CLOAD = 250pF CLOAD = 250pF Referenced to VPP Parameter Min Typ Max Units Conditions
Logic and Linear Inputs VDIN0-3(hi), VEN(hi) VDIN0-3(lo), VEN(lo) TEN(ON) TEN(OFF) IDIN0-3 ILIN Duty Cycle D D D D D D Duty cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle 16 75 16 75 100 20 80 20 80 24 85 24 85 0 % % % % % % VLIN = 0.9V, DIN = 0000 VLIN = 2.1V, DIN=0000 VLIN = 0V, DIN = 0011 VLIN = 0V, DIN = 1100 VLIN = 0V, DIN = 0000 VLIN = 0V, DIN = 1111 Logic input voltage, high 0.7xVDD 0 0 200 -1 V ---
Logic input voltage, low Enable to gate turn on delay Enable to gate turn off delay Digital input pull down resistance Linear control input current
330 -
0.3xVDD 150 150 460 1
V ns ns k uA
--LIN = VDD, DIN0 - DIN3 = 1111 LIN = VDD, DIN0 - DIN3 = 1111 ---40C to +85C
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HV7100
Pin Description
VDD - Output of an internal linear voltage regulator, which in turn is powered by VPP. It provides power to the internal low-side (ground referenced) circuitry. An external voltage may be applied to this pin, provided it is higher than 3.6V but less than 5.5V. Bypass this pin with a 100nF ceramic capacitor to ground. VPP1 & VPP2 - Supply voltage pins. Both must be connected to the supply voltage (+24V/+48V). Connect together as close as possible to the IC. Bypass locally with a ceramic capacitor to ground. OUT - This pin is the output gate driver for an external Pchannel power MOSFET.
VDD OUT
RT - In conjunction with CT, a resistor from this pin to ground sets PWM frequency. VGATE - This is the output pin of the internal linear regulator that biases the gate drive circuit. Bypass with 100nF ceramic capacitor to VPP. EN - Enable input. A logic high applied to this input enables the output.
Pinout
GND - Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train and logic return. LIN - A DC voltage ranging from 0.5V to 2.5V sets the duty cycle of the gate output from 0% to 100%. This input is immune to moderate noise on the control signal. DIN0 - DIN3 - Applying 0000 to 1111 to these logic input pins sets the duty cycle of the gate output from 0% to 100%. A 1-bit increment is equal to 6.67% increment in duty cycle. See Table 1 on page 5. CT - In conjunction with RT, a capacitor from this pin to ground sets PWM frequency. A triangle wave appears on this pin, with an amplitude of 0.5V - 2.5V and at the PWM frequency.
LIN DIN0 DIN1 DIN2 DIN3 EN
HV7100
VPP2 VPP1
VGATE RT CT GND
14-Lead SO (NG) Package
VPP
VDD
powered by VDD - Gnd
VPP1
powered by VPP - VGATE
VPP2
DIN0-3
DAC
3.3V
Reg
ideal diodes
LIN CT RT
UVLO OUT
level translator
ramp gen EN
Reg
VGATE
GND
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HV7100
Functional Description
The HV7100 requires a single +16V to +75V supply to bias its internal circuitry. It internally generates 3.3V for VDD, and -12V relative to VPP for driving the external P-channel MOSFET. If an external VDD is applied (greater than 3.6V but less than 5.5V), the internal regulator will shut off. The HV7100 drives an external P-channel FET to drive the 24V/48V DC fan. An external diode, connected across the fan terminals, is required to clamp the voltage across the fan to a diode drop during the off period. Linear control voltage below 0.5V will turn off the fan completely (0% duty cycle), while voltage greater than 2.5V will fully turn the fan on (100% duty cycle). When using linear control mode, DIN0 - DIN3 should be set to logic 0. If desired, DIN may be used to set a lower limit on the fan speed. This input is immune to moderate noise on the control signal. Digital Control - Applying logic signals to the DIN0 - DIN3 pins sets the duty cycle of the output. 0000 = 0% and 1111 = 100%. See Table 1 for details. In digital control mode, LIN should be set to 0V. DIN0 - DIN3 pins have internal pull downs so that the DAC output will default to 0V when it is not used. External PWM - An external PWM signal can be applied to the Enable pin to directly control the duty cycle. A logic 0 turns the transistor off, and a logic 1 turns it on. When using this control method, connect DIN0 - DIN3, LIN, and RT to VDD. Connect CT to GND. The DAC output and the Linear Control signals are OR'd together. Whichever has the higher value dominates. This allows an analog temperature sensing circuit to override the digital inputs (DIN0 - DIN3) for added system protection. The following table illustrates the correlation between the digital inputs and LIN voltage to the PWM duty cycle.
Pulse Width Modulator
The PWM circuit compares the internal triangle wave oscillator (0.5V - 2.5V pk-pk) with the linear control voltage or the DAC output. Its output is a square-wave PWM signal with duty cycle ranging from 0% to 100%. When an external PWM signal is applied to the Enable input and the internal PWM generator is not needed, RT and LIN should be connected to VDD and CT connected to GND.
Oscillator
A capacitor connected between the CT and GND sets the frequency of the internal triangular frequency oscillator in conjunction with the timing resistor RT. RT sets the charge/ discharge current into and out of CT. The frequency is determined by the following equation:
f=
0.258 RT CT
P-Channel Gate Driver
The PWM output of the comparator circuit is level translated and is the input to the gate drive circuit. The gate drive circuit turns an external P-channel FET on and off by applying -12V and 0V (reference to VPP), respectively, between its gate and source. The -12V supply to the gate drive circuit is generated internally from VPP.
Table 1. DAC signal and LIN voltage to Duty Cycle Programming.
DIN3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DIN2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DIN1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DIN0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LIN 0.500V 0.633V 0.766V 0.900V 1.033V 1.167V 1.300V 1.433V 1.567V 1.700V 1.833V 1.967V 2.100V 2.233V 2.367V 2.500V Gate Drive Duty Cycle 0%* 6.7% 13.3% 20.0% 26.7% 33.3% 40.0% 46.7% 53.3% 60.0% 66.7% 73.3% 80.0% 86.7% 93.3% 100%*
Enable
The EN pin directly controls the gate drive circuit. Pulling this pin to logic ground applies 0V to the external P-channel gate to turn it off. Applying a logic HIGH signal or pulling the voltage to VDD resumes the switching cycle of the PWM signal.
Speed Control
The fan speed can be controlled in three ways: Linear Control - Applying a DC voltage between 0.5V to 2.5V to the LIN pin varies the duty cycle of the voltage driving the fans from 0% to 100% according to:
D
V LIN 2
0.25
5
* Guaranteed 0% @ 0000 and 100% @ 1111
HV7100
PWM Fan Drive
VPP
VPP1 D3 D2 D1 D0
VPP2 VGATE
VDD
HV7100
EN LIN CT RT VDD GND OUT
When using direct PWM drive to the fans, it is best to set a low PWM frequency, in the range of 50Hz -120Hz.
DC Fan Drive
VPP
VPP1
VPP2
VGATE DIN0 - DIN3
HV7100
EN LIN OUT CT RT VDD GND
The addition of an LC low pass filter converts the PWM output to a DC voltage.
The HV7100 controls the fans with a PWM supply voltage. However, some fans require a steady DC voltage for proper operation. In order for these fans to function properly, an LC low pass filter should be added to cancel the PWM output to a steady DC voltage.
The LC filter also provides another advantage. Some fans draw large spikes of current during start-up and/or during normal operation. Without the LC filter, these current spikes would be drawn directly from the +24V or +48V supply, causing potential conducted EMI problems. The LC filter prevents these spikes from occuring and/or reaching the +24V or +48V supply.
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HV7100
Setting a Lower Speed Limit
VPP
VPP1 D3 D2 D1 D0
VPP2 VGATE
VDD
HV7100
EN LIN CT RT VDD GND OUT
When using the linear control input, the digital control inputs may be used to set a lower limit on the duty cycle. This is based on the fact that the higher control setting, linear
or digital, dominates. In the example above, duty cycle is prevented from falling below 25% even if the linear control signal goes to 0V.
14-LEAD SO PACKAGE (NG) (NARROW BODY)
8.65 - 0.10
Linear dimensions in millimeters. Angular dimensions in degrees. Pin 1 identifier may be a dot or chamfered edge, or both.
0.31 - 0.51
C L
3.90 - 0.10
C L
6.00 - 0.20
Pin 1 dot area
Top View
0.25 - 0.50 1.75 max 1.25 min 0.10 - 0.25 5 - 15 (4 plcs)
1.27 BSC
0.17 - 0.25
0.40 - 1.27
0 -8
Side View
End View
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in such applications, unless it receives an adequate "product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http//www.supertex.com.
(c)2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 / FAX: (408) 222-4895
Doc.# DSFP - HV7100 NR051506
www.supertex.com
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